systemverilog assertion without using dist

Neter

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23-11-2024

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SystemVerilog Assertions (SVAs) are a powerful mechanism for verifying the behavior of digital designs. They allow you to specify properties that must hold true during simulation, helping catch bugs early in the design process. While the dist (distributed) operator is often used for concisely expressing properties across multiple clocks or cycles, it's entirely possible and often preferable to write effective assertions without it, especially for clarity and maintainability. This article explores how to achieve this.

Why Avoid dist?

The dist operator, while powerful, can lead to assertions that are harder to understand and debug. Complex dist expressions can become opaque, obscuring the underlying logic. Furthermore, simulators might handle dist differently, leading to portability issues. Avoiding dist leads to more readable and maintainable code.

Alternatives to dist

Several techniques can replace the functionality of dist without sacrificing expressiveness:

1. Sequential Assertions with next

For properties that need to check across consecutive cycles, the next operator provides a clean alternative. It allows you to refer to the value of a signal in the next clock cycle.

property my_property;
  @(posedge clk) disable iff (reset)
    a == 0 |-> nextcycle (b == 1);
endproperty

assert property (my_property);

This assertion checks that if a is 0 in the current cycle, b will be 1 in the next cycle. This approach is clear and easy to follow, avoiding the potential complexity of dist.

2. Using always Blocks and Internal Signals

For more complex scenarios, an always block can be used to track relevant signals and combine them into a boolean condition checked by a simple assertion. This offers fine-grained control and improved readability.

reg condition;
always @(posedge clk) begin
  if (reset)
    condition <= 0;
  else if (a == 0)
    condition <= (b == 1);
  else
    condition <= condition; // Maintain previous value
end

assert property (@(posedge clk) disable iff (reset) condition);

Here, the always block calculates condition based on a and b, which is then directly asserted. This separates the logic from the assertion, improving code organization.

3. Concatenation and Sequencing

For properties involving multiple signals, concatenation and sequencing operators can be used to combine signals into a single value for comparison. This can replace some uses of dist that group signals across cycles.

property combined_signal;
  @(posedge clk) disable iff (reset)
    {a, b} == 2'b01; // check if a is 0 and b is 1
endproperty

assert property (combined_signal);

4. Multiple Assertions

Sometimes, a complex property expressed with dist can be broken down into smaller, simpler assertions that are easier to understand and maintain. This approach enhances modularity and debuggability.

Example: Detecting a Specific Sequence

Let's consider an example where we want to assert that the sequence 101 appears on signal x. While a dist-based solution might exist, a simpler approach using next and sequencing makes the intent more clear.

property sequence_101;
  @(posedge clk) disable iff (reset)
    x == 1 ##1 x == 0 ##1 x ==1;
endproperty

assert property (sequence_101);

This directly specifies the desired sequence without requiring the abstraction of dist.

Conclusion

While the dist operator offers a concise way to express certain properties, it's not always the best choice. Prioritizing readability and maintainability often leads to simpler, more robust assertions. Using techniques like next, always blocks, concatenation, and breaking down complex properties into smaller assertions allows you to write effective SystemVerilog Assertions without relying on dist, leading to clearer, more maintainable verification code. Remember to always prioritize code clarity and ease of debugging when designing your verification strategy.